Generic VHDL Reversible Logic Gate Libraries and Evaluation of Digital Circuits as Custom IP Accelerators

Programming Languages UsedVHDL, C/C++
IDE / ToolsModelsim, Xilinx ISE, Xilinx XPS, QT4, yEd Editor
Other TagsMicroblaze soft-core processor, AXI Interface, PLB Interface, Custom IPs, Custom Libraries, Reversible Logic

This is my Master Project with the full name “Design, Implementation and Testing of Generic VHDL Reversible Logic Gate Libraries and Evaluation of Digital Circuits as Custom IP Accelerators”.

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The presentation can be viewed here:

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