FPGA-Prototype of a Tomasulo Dynamic Scheduling Unit based on Reversible Computing

Programming Languages usedVHDL [Hardware Description]
IDE ToolsMentor Graphics Modelsim, Xilinx ISE
Architecture ImplementedTomasulo Algorithm/Tomasulo Dynamic Scheduling Hardware Architecture
Technologies usedStandard digital logic and Reversible Computing Logic [Tofolli gates, Fredkin etc.]

Summary of Objectives:


The objectives of the thesis are summarized as follows:
1. Study of dynamic scheduling: Tomasulo Algorithm
• Exploring the hardware organization of Tomasulo Algorithm.
• Study of different concepts associated with dynamic scheduling such as
data and control hazards.
2. Implementation of Tomasulo Unit using VHDL
Alteration of Tomasulo architecture to exclude irrelevant components
such as Store/Load Units.
• Simulating the design units using individual testbenches for each component.
• Simulation and Test of the whole system using top level testbench .
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3. Design of a dynamic scheduling unit based on reversible logic
• Design of reversible logic data unit with associated controls lines.
• Proving and testing the reversibility of the reversible unit with test
benches.
• Simulating the aforementioned block with manual a program code.
• Writing control algorithm for dynamic scheduling based on Tomasulo
algorithm.
• Simulating and testing with top level testbenches.
The VHDL based design and FPGA implementation are not purely reversible, but the focus is more on simulation and emulation to demonstrate how a
reversible unit might work when studied under the light of dynamic scheduling

These document relate to my Master Thesis with complete description.

Note: Embedded PDF documents allow respective pptx downloads for better viewing e.g. with animation

The report can be viewed in the following pdf Embedding [alternatively on Docdroid: Here]

The presentation PDF can be viewed in the embedded box below:

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